The present invention generally relates to a method for bonding a semiconductor chip to a circuit board and more particularly, relates to a method for direct chip attach of a semiconductor chip to a circuit board by solder bumps on the chip, conductive pads on the circuit board and a flux-containing underfill layer thereinbetween.
In modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such devices. Conventionally, a flip-chip attachment method has been used in the packaging of IC chips. In the flip-chip attachment method, instead of attaching an IC die to a lead frame in a package, an array of solder balls is formed on the surface of the die. The formation of the solder balls is normally carried out by an evaporation method of lead and tin through a mask for producing the desired solder balls. More recently, the technique of electro-deposition has been used to produce solder balls in flip-chip packaging.
Other solder ball formation techniques that are capable of solder-bumping a variety of substrates have been proposed. These techniques work well in bumping semiconductor substrates that contain solder structures over a minimum size. One of the more popularly used techniques is a solder paste screening technique which can be used to cover the entire area of an eight inch wafer. However, with the recent trend in the miniaturization of device dimensions and the reduction in bump-to-bump spacing (or pitch), the solder paste screening technique becomes impractical. For instance, one of the problems in applying solder paste screening technique to modern IC devices is the paste composition itself. A paste is generally composed of a flux and solder alloy particles. The consistency and uniformity of the solder paste composition become more difficult to control with a decreasing solder bump volume. A possible solution for this problem is the utilization of solder pastes that contain extremely small and uniform solder particles. However, this can only be achieved at a high cost penalty. Another problem in using the solder paste screening technique in modern high density devices is the reduced pitch between bumps. Since there is a large reduction in volume from a screened paste to the resulting solder bump, the screen holes must be significantly larger in diameter than the final bumps. The stringent dimensional control of the bumps makes the solder paste screening technique impractical for applications in high density devices.
A more recently developed injection molded solder (IMS) technique attempted to solve these problems by dispensing molten solder instead of solder paste. However, problems have been observed when the technique is implemented to wafer-sized substrates. U.S. Pat. No. 5,244,143, discloses the injection molded solder technique and is hereby incorporated by reference in its entirety. One of the advantages of the IMS technique is that there is very little volume change between the molten solder and the resulting solder bump. The IMS technique utilizes a two-inch wide head that fills borosilicate glass molds that are wide enough to cover most single chip modules. A narrow wiper provided behind the solder slot passes the filled holes once to remove excess solder. The IMS method for solder bonding is then carried out by applying a molten solder to a substrate in a transfer process. When smaller substrates, i.e., chip scale or single chip modules (SCM""s) are encountered, the transfer step is readily accomplished since the solder-filled mold and substrate are relatively small in area and thus can be easily aligned and joined in a number of configurations. For instance, the process of split-optic alignment is frequently used in joining chips to substrates. The same process may also be used to join a chip-scale IMS mold to a substrate (chip) which will be bumped.
A more recently developed method that alleviated the limitations of the solder paste screening technique of significant volume reductions between the initial paste and the final solder volume is the molten solder screening (MSS) method. In the MSS method, pure molten solder is dispensed. When the MSS solder-bumping method is used on large substrates such as eight inch or twelve inch wafers, surface tension alone is insufficient to maintain intimate contact between a mold and a substrate. In order to facilitate the required abutting contact over large surface areas, a new method and apparatus for maintaining such are necessary.
For instance, in a copending application of Attorney Docket No. Y0997-216 commonly assigned to the Assignee of the present application and is hereby incorporated by reference in its entirety, a method for forming solder bumps by a MSS technique that does not have the drawbacks or shortcomings of the conventional solder bumping techniques has been proposed. In the method, a flexible die member is used in combination with a pressure means to enable the die member to intimately engage a mold surface and thus filling the mold cavities and forming the solder bumps. The flexible die head also serves the function of a wiper by using a trailing edge for removing excess molten solder from the surface of the mold.
The MSS process can be carried out by first filling a multiplicity of cavities in the surface of a mold with molten solder. This is accomplished by first providing a stream of molten solder and then passing a multiplicity of cavities in the mold surface in contact with the surface of the stream while adjusting a contact force such that the molten solder exerts a pressure against the surface of the mold to fill the cavities with solder and to remove excess solder from the surface of the mold. The stream of molten solder is supplied through a die head constructed of a flexible metal sheet that is capable of flexing at least 0.0015 inches per inch of the die length. The solder has a composition between about 58% tin/42% lead and about 68% tin/32% lead. The multiplicity of cavities each has a depth-to-width aspect ratio of between about 1:1 and about 1:10. The mold body is made of a material that has a coefficient of thermal expansion substantially similar to that of silicon or the final solder receiving material. The contact between the multiplicity of cavities and the surface of the molten solder stream can be adjusted by a pressure means exerted on the flexible die.
The MSS method is therefore a new technique for solder bumping large eight inch or even twelve inch silicon wafers. As previously described, the technique involves filling cavities in wafer-sized mold plates with molten solder, solidifying the solder and then transferring the solder in these cavities to the wafer. The transfer process requires aligning the cavities in a mold plate to the solder receiving pads on a silicon wafer and then heating the assembly to a solder reflow temperature. This results in the molten solder metallurgically bonding to the metallized pads on the wafer and thus assuring the solder in each cavity to transfer from the mold plate to the wafer. Since various solder alloys are readily processed with the MSS technique, the mold plate and wafer assembly must remain aligned throughout the reflow process. Since the contact area between mold plate and wafer covers an entire eight inch or twelve inch silicon wafer, it is important that these materials match very closely in coefficient of thermal expansion (CTE), i.e., the mold plate may be fabricated of a borosilicate glass.
In another copending application assigned to the common assignee of the present invention, Attorney Docket No. Y0997-273, a process for etching a glass mold plate is disclosed for producing the desired cavities in a mold for receiving molten solder. However, since glass is an amorphous material, processing parameters which control isotropic etching must be carefully monitored to produce the desired cavity volumes. Even when such control is possible, the resulting cavity is hemispherical in shape which allows the reflowed solder ball certain degree of lateral movement before bonding to the solder receiving pad on a wafer or any other electronic substrates. It is desirable to eliminate any possibility of such lateral movement so that highest accuracy of ball location during the reflow process can be maintained.
In still another copending application assigned to the common assignee of the present invention, Attorney Docket No. Y0998-216, hybrid molds for molding a multiplicity of solder balls which are constructed by a crystalline silicon face plate provided with a multiplicity of cavities formed in a front surface and a rigid backing plate which has substantially the same coefficient of thermal expansion as crystalline silicon for bonding to a back surface of the face plate and a method for preparing such molds are disclosed. In the construction of the hybrid molds, a complicated procedure is used to securely bond a silicon face plate to a rigid backing plate by injecting an adhesive into a gap formed between the two plates. The method is costly and time consuming.
In a conventional flip chip process, an underfill material that is CTE matched to solder by using fillers in the underfill composition is frequently dispensed after chip-substrate attach by a capillary action through the gap between the chip and the substrate. The distance between the chip and the substrate is typically between 75xcx9c125 xcexcm. The conventional underfill dispensing process is a time consuming process which affects the yield of the fabrication process. Attempts have been made to reduce the fill time for the underfill material by the dispensing a flux-containing underfill on the substrate""s chip site prior to a chip-substrate attach process. However, in order to permit fluxing action of the chip""s solder bumps to the substrate pads through the entire thickness of the underfill, i.e., 75xcx9c125 xcexcm, the amount of filler material that can be added into the underfill composition is limited. As a consequence, the CTE of the underfill composition cannot be lowered to a desirable level, i.e., 20xcx9c25 ppm/xc2x0 C. or a level that is close to that of solder. The process therefore presents limited reliability enhancement and is inadequate for many chip-on-laminate applications.
In still another copending application assigned to the common assignee of the present invention and filed on the same date of the present invention, Attorney Docket No. Y0998-197 which is incorporated hereby in its entirety by reference, a method for forming solder bumps directly on a wafer surface by utilizing a screen printable polymeric layer as a solder mold and then plating a solder material into the cavities overlying conductive pads is disclosed. A mechanical fixture for bumping direct-on-wafer solder bumps by a molten solder screening technique is also disclosed. The method allows a wafer to be solder bumped with an in-situ mold by the molten solder screening technique and therefore eliminates the need for a separate mold. The solder fills the in-situ mold holes to the same level as the top surface of the mold layer, i.e., about 2xcx9c3 mils above the surface of the silicon wafer. After the solder solidifies, the wafer is ready to be diced into chips. Since the solder is contained within the mold cavities, it is much more resistant to damage than solder balls that normally protrude above the surface. After the initial solder deposition, there is only one reflow process required to transfer the chips to the laminate substrate.
Still others have suggested a method of first applying a B-stage epoxy film on the chip surface which has the same thickness as the solder bumps, i.e., 75xcx9c125 xcexcm. The epoxy film, placed on the chip after the solder bumps, has some of the same processing difficulties as the approach of using flux-containing underfill materials on the substrate""s chip site. Furthermore, a temporary chip attach for burn-in could not be effected without fully curing the epoxy film and thus making any subsequent removal process difficult, if not impossible.
It is therefore an object of the present invention to provide a method for bonding a semiconductor chip to a circuit board that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for bonding a semiconductor chip to a circuit board by utilizing solder bumps planted on the surface of the chip and an underfill layer disposed on the surface of the circuit board.
It is a further object of the present invention to provide a method for bonding a semiconductor chip to a circuit board by forming bonds between a first multiplicity of solder bumps on the chip and a second multiplicity of conductive pads on the circuit board by an underfill layer disposed thereinbetween.
It is another further object of the present invention to provide a method for bonding a semiconductor chip to a circuit board by first providing a polymeric based in-situ solder mold, with CTE properties within the range of that of the semiconductor chip and that of the solder, on the top surface of the chip and then filling the mold with a solder material for forming solder bumps that are used for bonding to conductive pads on a circuit board.
It is still another object of the present invention to provide a method for direct chip attach by solder bumps and an underfill layer wherein a flux-containing underfill material is utilized for bonding between the semiconductor chip and the circuit board.
It is yet another object of the present invention to provide a method for direct chip attach by solder bumps and an underfill layer in which a thin layer of flux-containing underfill material of less than 5 xcexcm thickness is used between a chip and a circuit board.
It is still another further object of the present invention to provide an electronic assembly that includes a semiconductor chip that has a top surface overlied by a polymeric in-situ mold of appropriate mechanical properties for solder fatigue enhancement (3xcx9c30 ppm/xc2x0 C.) containing a multiplicity of solder bumps therein and a circuit board which has a top surface formed with a multiplicity of conductive pads bonded together by a flux-containing underfill layer inbetween.
It is yet another further object of the present invention to provide an electronic assembly which incorporates composite underfill layer consisting of a polymeric in-situ mold layer and a flux-containing underfill material layer.
In accordance with the present invention, a method for bonding a semiconductor chip to a circuit board by a direct chip attach technique utilizing solder bumps and an underfill layer is provided.
In a preferred embodiment, a method for bonding a semiconductor chip to a circuit board by solder bumps and an underfill layer can be carried out by the steps of first providing a semiconductor chip that has a top surface formed with a first multiplicity of conductive pads, coating a layer of insulating material having a first multiplicity of apertures on the top surface of the semiconductor chip exposing the first multiplicity of conductive pads, the layer of insulating material has a thickness substantially similar to a thickness of the solder bumps to be planted and CTE between 3xcx9c30 ppm/xc2x0 C., depositing a ball-limiting-metallurgy layer in the first multiplicity of apertures overlying the first multiplicity of conductive pads, filling the first multiplicity of apertures with a solder material forming a first multiplicity of solder bumps, providing a circuit board which has a second multiplicity of conductive pads formed in a top surface positioned in mirror image to the first multiplicity of conductive pads on the semiconductor chip, disposing a layer of a flux-containing underfill material on the top surface of the circuit board, and engaging the top surface of the circuit board and the top surface of the semiconductor chip together with the first multiplicity of conductive pads intimately contacting the second multiplicity of conductive pads through the layer of underfill material, and heating to a temperature sufficient to establish electrical communication between the first multiplicity and the second multiplicity of conductive pads.
In the method for bonding a semiconductor chip to a circuit board by solder bumps and an underfill layer, the step of providing a semiconductor chip may further include a step of providing a silicon wafer which has a plurality of semiconductor chips formed on a top surface. The layer of insulating material coated on the top surface of the semiconductor chip is an in-situ mold for molding a first multiplicity of solder bumps in the first multiplicity of apertures. The layer of insulating material may be a polymeric material that can be patterned in a photolithographic process, or a polyimide material that is photo-sensitive or processable by laser ablation. The layer of insulating material has a CTE of 3xcx9c30 ppm/xc2x0 C.
In the method for bonding a semiconductor chip to a circuit board, the BLM layer may include at least two sub-layers selected from the group consisting of an adhesion layer, a diffusion barrier layer and a wetting layer. The BLM layer may be deposited by a physical vapor deposition technique (including but not limited to evaporation or sputtering), an electroless or electrolytic plating technique. The step of depositing the BLM layer may further include steps of masking and/or removing by etching away the BLM layer that is not situated in the first multiplicity of apertures. The step of filling the first multiplicity of apertures with a solder material may be carried out by an electrodeposition, an electroless deposition technique or MSS technique. The method may further include the step of coating the second multiplicity of conductive pads with a BLM layer prior to the positioning step for the layer of the fluxed underfill material.
In the method for bonding a semiconductor chip to a circuit board by a direct chip attachment technique, the layer of underfill material is disposed on the top surface of the circuit board to a thickness of not more than 15 xcexcm, or to a thickness between about 5 xcexcm and about 15 xcexcm. The layer of insulating material on the wafer may have a thickness of not less than 20 xcexcm, or a thickness between about 20 xcexcm and about 200 xcexcm. The layer of insulating material on the wafer may further have a CTE between 3xcx9c30 ppm/xc2x0 C. The layer of underfill material may further include a surface-enhancing agent, or a surface wetting agent. The step of heating the semiconductor chip and the circuit board to a temperature sufficient to establish electrical communication does not cause the formation of solder balls from the first multiplicity of solder bumps.
The present invention is further directed to an electronic assembly which includes a semiconductor chip that has a top surface overlayed by a layer of insulating material and containing a first multiplicity of via openings each filled with a solder bump on top of a bond pad, and a circuit board which has a top surface formed with a second multiplicity of conductive pads positioned in a mirror image relationship with the first multiplicity of via openings on the semiconductor chip, the top surface of the circuit board intimately joins the top surface of the semiconductor chip with an underfill layer disposed thereinbetween such that electrical communication between the first multiplicity of via openings filled with the solder bumps and the corresponding second multiplicity of conductive pads is established.
In the electronic assembly, the layer of insulating material overlying the top surface of the semiconductor chip is formed of a photo-sensitive polymeric material. The layer of insulating material overlying the top surface of the semiconductor chip is formed of a material that is patterned by a photolithographic process. The layer of insulating material overlying the top surface of the semiconductor chip is an in-situ mold for the first multiplicity of solder bumps. The layer of insulating material on the wafer may have a thickness of between about 20 xcexcm and about 200 xcexcm. The layer of insulating material on the wafer may further have a CTE between 3xcx9c30 ppm/xc2x0 C. Each of the multiplicity of via openings may further include a BLM layer disposed between the solder bump and the bond pad. The BLM layer may include at least two sublayers selected from the group consisting of an adhesion layer, a diffusion barrier layer and a wetting layer. The underfill layer may further include a surface enhancing agent or a wetting agent. The underfill layer disposed between the semiconductor chip and the circuit board may have a thickness of not more than 15 xcexcm.
In an alternate embodiment, a method for direct chip attach (DCA) by solder bumps and underfill layer can be carried out by the operating steps of first providing a semiconductor chip equipped with a first multiplicity of bond pads on a top surface, then coating the top surface with a photo-sensitive polymeric material layer, patterning the photo-sensitive polymeric material layer by a photolithographic method to form a first multiplicity of via openings exposing the first multiplicity of bond pads, filling the first multiplicity of via openings with a solder material forming solder bumps, providing a circuit board equipped with a second multiplicity of conductive pads on top, the second multiplicity of conductive pads is formed in a mirror image to the first multiplicity of bond pads on the semiconductor chip, disposing a flux-containing underfill layer on top of the circuit board, and bonding under heat the first multiplicity of bond pads to the second multiplicity of conductive pads to establish electrical communication with the flux-containing underfill layer thereinbetween.
The method for direct chip attach by solder bumps and underfill layer may further include the step of bonding the first multiplicity of bond pads to the second multiplicity of conductive pads at a temperature higher than a melting point of the solder material. The photo-sensitive polymeric material layer maybe formed of polyimide. The photo-sensitive polymeric material layer may have a thickness of between about 20 xcexcm and about 200 xcexcm. The flux-containing underfill layer may have a thickness not more than 15 xcexcm.